The present invention relates to a multilayer build-up wiring board having build-up wiring layers each consisting of interlayer resin insulating layers and conductor layers provided alternately on both sides of a core substrate. The present invention relates to, in particular, a multilayer build-up wiring board provided with plane layer formed as a power conductor layer (power layer) or as a ground conductor layer (ground layer).
To reduce noise and the like, one layer of a conductor circuit is used as a ground layer or a power layer in a multilayer build-up wiring board having a plurality of conductor layers (conductor circuits) isolated by interlayer resin insulating layers, respectively. In the multilayer build-up wiring board, as shown in FIG. 9C, a plain layer 559 forming a ground conductor layer (ground layer) or a power conductor layer (power layer) is often formed into a mesh pattern having mesh holes 559a. The reason for providing the mesh holes 559a is as follows. Since the plain layer 559 is formed of copper having a low connection property for connecting with resin, the connection between an upper layer or an interlayer resin insulating layer (not shown) and a lower layer or a resin core substrate (not shown) is improved by directly connecting the interlayer resin insulating layer to the core substrate with the mesh holes 559a. In addition, it is intended to make it easy for gas containing moisture and the like absorbed by the interlayer resin insulating layer to exhale through the mesh holes 559a. 
As for the positions for forming these mesh hole 559a, there are various proposals made. For example, Japanese Patent Unexamined Application Publication No. 1-163634 proposes, as shown in FIG. 9B, a technique for providing the penetrating holes 559a of an upper plain layer 559 and mesh holes 559a of a lower plain layer 559B so as not to overlap one another by shifting the positions of the penetrating holes 559a of the upper plain layer 559 and those of the mesh holes 559a of the lower plain layer 559B from one another to thereby prevent recessed portions from being formed on the surface of a board.
An interlayer resin insulating layer separating conductor layers is required to have high insulating property. The inventor of the present invention discovered that the insulating property of the interlayer resin insulating layer correlates to the relative positional relationship between the penetrating holes formed on the upper and lower plain layers. Then, a multilayer build-up wiring board is formed while the positions of the penetrating holes are adjusted, and the insulating property of the interlayer resin insulating layer is measured. As a result, the present inventor reached a conclusion that if the penetrating holes 559a of the upper plain layer 559 are shifted from the mesh holes 559a of the lower plain layer 559B as shown in FIG. 9B, the insulating property of the interlayer resin insulating layer greatly deteriorates.
The present invention has been made to solve the above-stated disadvantage. One object of the present invention is to provide a multilayer build-up wiring board provided with a plain layer and having the less deterioration of the insulating property of the interlayer resin insulating layer.
Meanwhile, as for the positions at which these mesh holes are formed, various proposals have been made. For example, Japanese Patent Unexamined Application Publication No. 10-200271 proposes a technique, as shown in FIG. 23, that mesh holes are not provided in a region of a plain layer 559 facing a chip mount region indicated by C and only provided in a region outside the chip mount region, thereby preventing irregular portions from being provided in the chip mounting region to thereby make the chip mount region flat on a multilayer printed circuit board.
As stated above, gas contained in the interlayer resin insulating layer is exhaled through the mesh holes. If no mesh hole is provided in the chip mount region as in the above technique, moisture does not exhale from an interlayer resin insulating layer below the chip mount region. Then, the interlayer resin insulating layer is peeled off or the insulation resistance of the interlayer resin insulating layer deteriorates.
The present invention has been made to solve the above disadvantage and its still further object is to provide a multilayer build-up wiring board having less insulation deterioration of the interlayer resin insulating layer and capable of forming a flat chip mount region.
Meanwhile, a multilayer build-up wiring board forming a package board for mounting an IC chip and the like is formed by alternately building up interlayer resin insulating layers and conductor layers on a core board provided with through holes and by providing connection bumps for connecting to the IC chip on the upper surface side and bumps for connecting to a mother board on the lower surface side. Then, the upper and lower conductor layers are-connected by forming via holes and the via holes on the upper layer of the core board and those on the lower layer thereof are connected to one another by a through hole.
However, the via holes are formed by providing non-penetrating holes in the interlayer resin insulating layers. Due to this, the number of via holes of a fixed size to be formed in the multilayer build-up wiring board is physically limited, which is one of the factors disadvantageously preventing high concentration of the via holes in the multilayer build-up wiring board.
The present invention has been made to solve the above disadvantage and its still further object is to provide a multilayer build-up wiring board capable of providing wirings with high concentration.
Further, as a technique for a multilayer build-up wiring board using a resin board, for example, Japanese Patent Examined Application Publication No. 4-55555 proposes a method of forming epoxy acrylate on a glass epoxy board, on which circuits are mounted, as interlayer resin insulating layers, providing opening portions for via holes using photolithography, roughening the surface, providing a plating resist and thereby forming conductor circuits and via holes by plating.
Conventionally, after the conductor circuits and via holes are formed by the above method, a roughened layer made of Cuxe2x80x94Nixe2x80x94P alloy for coating the conductor circuits and the like is formed by electroless plating and an interlayer resin insulating layer is formed thereon.
However, if fabricated printed circuit boards are subjected to a heat cycle test or the like, some of them cannot be used as a multilayer build-up wiring board because cracks occur from the corners of an upper layer conductor circuit through the interlayer resin insulating layer and the cracks spread toward the upper surface of the board and a lower layer conductor circuit resulting from the difference in heat expansion between the upper layer conductor circuit made of metal and the interlayer resin insulating layer made of resin.
The reason the cracks occur is, it appears, that the corners of the upper layer conductor circuit tend to be sharpened and stress is concentrated on the corners by the expansion and compression due to the temperature change of the upper layer conductor circuit.
The present invention has been made to solve the above disadvantage of the conventional technique and a still further object is to provide a wiring board and a multilayer build-up wiring board capable of preventing the concentration of stress derived from the change of temperature of the corners of the formed conductor circuit and preventing the resin insulating layer from cracking.
To obtain the above objects, a multilayer build-up wiring board recited in claim 1 is a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, technically characterized in that
a plurality of plain layers (which function as power conductor layers or ground conductor layers) are formed as the conductor layers; and
mesh holes are formed in the plurality of plain layers so that at least part of the mesh holes overlay one another.
A multilayer build-up wiring board recited in claim 2 is a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, technically characterized in that
plain layers (serving as power conductor layers or ground conductor layers) are formed as conductor layers at least one side of the core substrate;
a plain layer is formed out of at least one of the conductor layers formed between the interlayer resin insulating layers; and
mesh holes are formed in the plain layer of the core substrate and the plain layer between the interlayer resin insulating layers so that at least part of the mesh holes overlay one another.
According to claim 3, the multilayer build-up wiring board according to claim 1 or 2, is characterized in that
a diameter of each of said mesh holes is set at 75 to 300 xcexcm and a distance between the mesh holes is set at 100 to 1500 xcexcm.
According to claim 1, the mesh holes of the upper and lower plain layers are formed such that at least part of them overlay one another, thereby preventing the insulating properties of the interlayer resin insulating layers from greatly deteriorating.
Here, the diameter of each mesh hole is preferably 75 to 300 xcexcm. The reason is as follows. If the diameter is less than 75 xcexcm, it is difficult to overlay upper and lower mesh holes on one another. If it exceeds 300 xcexcm, the conductor layers do not function as power conductor layers (power layers) or ground conductor layers (ground layers). In addition, the distance between the mesh holes is preferably 100 to 1500 xcexcm. The reason is as follows. If the distance is less than 100 xcexcm, the area of the plain layer becomes small and the plain layer cannot function. If the distance exceeds 1500 xcexcm, the degree of deterioration of insulating properties of the interlayer resin insulating layers becomes considerably high.
In the present invention, it is desirable to use an adhesive for electroless plating as the above interlayer resin insulating layer. In this adhesive for electroless plating, it is optimal that heat resisting resin particles soluble to a hardened acid or oxidizing agent are dispersed into unhardened heat resisting resin which has difficult solubility to an acid or an oxidizing agent.
The heat resisting resin particles are dissolved and removed by processing these resin particles using an acid or an oxidizing agent, and a coarsened face constructed by an anchor formed in the shape of an octopus trap can be formed on a layer surface.
In the above adhesive for electroless plating, the above heat resisting resin particles particularly hardened are desirably constructed by using {circle around (1)} heat resisting resin powder having an average particle diameter equal to or smaller than 10 xcexcm, {circle around (2)} cohesive particles formed by aggregating heat resisting resin powder having an average particle diameter equal to or smaller than 2 xcexcm, {circle around (3)} a mixture of heat resisting powder resin powder having an average particle diameter from 2 to 10 xcexcm and heat resisting resin powder having an average particle diameter equal to or smaller than 2 xcexcm, {circle around (4)} pseudo-particles in which at least one kind of heat resisting resin powder or inorganic powder having an average particle diameter equal to or smaller than 2 xcexcm is attached to the surface of heat resisting resin powder having an average particle diameter from 2 to 10 xcexcm, {circle around (5)} a mixture of heat resisting powder resin powder having an average particle diameter from 0.1 to 0.8 xcexcm and heat resisting resin powder having an average particle diameter greater than 0.8 xcexcm and smaller than 2 xcexcm, and {circle around (6)} heat resisting powder resin powder having an average particle diameter from 0.1 to 1.0 xcexcm. This is because these materials can form a more complicated anchor.
A depth of the coarsened face is preferably set to secure a close attaching property such that Rmax=0.01 to 20 xcexcm. In particular, Rmax preferably ranges from 0.1 to 5 xcexcm in the semi-additive method since an electroless plating film can be removed while the close attaching property is secured.
The heat resisting resin which has difficult solubility to an acid or an oxidizing agent mentioned above is desirably constructed by xe2x80x9ca resin complex constructed by thermosetting resin and thermoplastic resin,xe2x80x9d or xe2x80x9ca resin complex constructed by photosensitive resin and thermoplastic resin.xe2x80x9d The former has a high heat resisting property. The latter is desirable since the opening for the via hole can be formed by photolithography.
The above thermosetting resin can be constructed by using epoxy resin, phenol resin, polyimide resin, etc. When the thermosetting resin is photosensitized, a thermosetting group acrylic-reacts on methacrylic acid, acrylic acid, etc. Acrylate of the epoxy resin is particularly optimal.
The epoxy resin can be constructed by using epoxy resin of novolak type such as phenol novolak type, cresol novolak type, etc., dicyclopentadiene-modified alicyclic epoxy resin, etc.
The thermoplastic resin can be constructed by using polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyether imide (PI), etc.
A mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is preferably set such that thermosetting resin (photosensitive resin)/thermoplastic resin=95/5 to 50/50. This is because a high toughness value can be secured without reducing a heating resisting property.
A mixing weight ratio of the above heat resisting resin particles is preferably set to range from 5 to 50 weight % and desirably range from 10 to 40 weight % with respect to the solid content of a heat resisting resin matrix.
The heat resisting resin particles are preferably constructed by amino resin (melamine resin, urea resin, guanamine resin), epoxy resin, etc.
The adhesive may be constructed by two layers having different compositions.
Various kinds of resins can be used as a solder resist layer added to a surface of the multilayer build-up wiring board. For example, it is possible to use bisphenol A-type epoxy resin, acrylate of bisphenol A-type epoxy resin, novolak type epoxy resin, resin formed by hardening acrylate of novolak type epoxy resin by an amine-system hardening agent, an imidazole hardening agent, etc.
There is a case in which such a solder resist layer is separated since the solder resist layer is constructed by resin having a stiff skeleton. Therefore, the separation of the solder resist layer can be also prevented by arranging a reinforcing layer.
The above acrylate of the novolak type epoxy resin can be constructed by using epoxy resin in which glycidyl ether of phenol novolak and cresol novolak reacts with acrylic acid, methacrylic acid, etc.
The above imidazole hardening agent is desirably formed in a liquid state at 25xc2x0 C. since the imidazole hardening agent can be uniformly mixed in the liquid state.
Such a liquid state imidazole hardening agent can be constructed by using 1-benzyl-2-methylimidazol (product name: 1B2MZ),1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ).
An adding amount of this imidazole hardening agent is desirably set to range from 1 to 10 weight % with respect to a total solid content of the above solder resist composition substance. This is because the imidazole hardening agent is easily uniformed and mixed if the adding amount lies within this range.
A composition substance prior to the hardening of the above solder resist is desirably constructed by using a solvent of a glycol ether system as a solvent.
In the solder resist layer using such a composition substance, no free acid is caused and no copper pad surface is oxidized. Further, a harmful property with respect to a human body is low.
Such a solvent of the glycol ether system is constructed by using the following structural formula, particularly desirable using at least one kind selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG). This is because these solvents can perfectly dissolve benzophenone and Michler""s ketone as reaction starting agents at a heating temperature from about 30 to 50xc2x0 C.
CH30xe2x80x94(CH2CH20)n -CH3 (n=1 to S)
This solvent of the glycol ether system preferably has 10 to 70 wt % with respect to a total weight amount of the solder resist composition substance.
As explained above, various kinds of antifoaming and leveling agents, thermosetting resin for improving a heat resisting property and an antibasic property and giving a flexible property, a photosensitive monomer for improving resolution, etc. can be further added to the solder resist composition substance.
For example, the leveling agent is preferably constructed by monomer of acrylic ester. A starting agent is preferably constructed by Irugacure 1907 manufactured by CHIBAGAIGI. A photosensitizer is preferably constructed by DETX-S manufactured by NIHON KAYAKU.
Further, a coloring matter and a pigment may be added to the solder resist composition substance since a wiring pattern can be hidden. This coloring matter is desirably constructed by using phthalocyaline green.
Bisphenol type epoxy resin can be used as the above thermosetting resin as an adding component. In this bisphenol type epoxy resin, there are bisphenol A-type epoxy resin and bisphenol F-type epoxy resin. The former is preferable when an antibasic property is earnestly considered. The latter is preferable when low viscosity is required (when a coating property is earnestly considered).
A polyhydric acrylic-system monomer can be used as the above photosensitive monomer as an adding component since the polyhydric acrylic-system monomer can improve resolution. For example, DPE-6A manufactured by NIHON KAYAKU and R-604 manufactured by KYOEISYA KAGAKU can be used as the polyhydric acrylic-system monomer.
These solder resist composition substances preferably have 0.5 to 10 Paxc2x7s in viscosity at 25xc2x0 C. and more desirably have 1 to 10 Paxc2x7s in viscosity since these solder resist composition substances are easily coated by a roll coater in these cases.
To obtain the above objects, according to claim 4, a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, provided with a chip mount region on which a chip is mounted on an outermost layer and having the conductor layers connected to each other by via holes, respectively characterized in that
mesh holes are provided in plain layers formed as said conductor layers, and lands of through holes or the via holes and the via holes are provided in at least part of mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
According to the invention recited in claim 4, mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and the land of a through hole or via hole and a pad to which a via hole is connected are provided in at least part of the mesh holes with a distance kept between the land and pad and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the mesh holes provided on the outer periphery of the land, thereby making it possible to increase bonding property. In addition, gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the land, so that the insulating properties of the interlayer resin insulating layers can be improved. Further, since the land and via hole are provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
Furthermore, according to claim 5, a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, provided with a chip mount region on an outermost layer and having the conductor layers connected to each other by via holes, respectively, is characterized in that
mesh holes are provided in plain layers formed as said conductor layers, and lands of the via holes are provided in at least part of the mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
According to the invention recited in claim 5, mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and the land of a via hole is provided in each of at least part of the mesh holes with a distance kept between the land of the via hole and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the mesh holes provided on the outer periphery of the land of the via hole, thereby making it possible to increase bonding property. In addition, gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the lands, so that the insulating properties of the interlayer resin insulating layers can be improved. Further, since a via hole is provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
According to claim 6, a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, provided with a chip mount region on an outermost layer is characterized in that
mesh holes are provided in plain layers formed as said conductor layers, and solid conductor layers are provided in at least part of mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
According to the invention recited in claim 6, mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and a solid conductor layer is provided in each of at least part of the mesh holes with a distance kept between the solid conductor layer and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the meshes provided on the outer periphery of the solid conductor layer, thereby making it possible to increase bonding property. In addition, gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the solid conductor layers, so that the insulating properties of the interlayer resin insulating layers can be increased. Further, since the solid conductor layer is provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
According to claim 7, a multilayer build-up wiring board wherein interlayer resin insulating layers and conductor layers are alternately provided on a substrate having through holes and a chip mount region for mounting a chip is provided on an outermost layer, is characterized in that
mesh holes are provided in plain layers formed as said conductor layers, and lands of the through holes are provided in at least part of mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
According to the invention recited in claim 7, mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and the land of a the through hole is provided in each of at least part of the mesh holes with a distance kept between the through hole and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the meshes provided on the outer periphery of the lands, thereby making it possible to increase bonding property. In addition, gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the lands, so that the insulating properties of the interlayer resin insulating layers can be increased. Further, since the land is provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
It is noted that the plain layer may face the chip mount region through at least one of the interlayer resin insulating layers according to the present invention.
To solve the above disadvantage, according to claim 8, a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, respectively, the multilayer wiring layer formed on a core substrate, is characterized in that
one of said via holes is formed out of a plurality of wiring paths.
On the multilayer build-up wiring board recited in claim 8, since one via hole consists of a plurality of wiring paths, several times as many wiring paths as. the via holes can be passed through the interlayer resin insulating layers, thereby making it possible to provide wirings on the multilayer build-up wiring board with high concentration.
According to claim 9, a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, respectively, the multilayer wiring layer formed on a core substrate, characterized in that
one of said via holes is formed out of two wiring paths.
On the multilayer build-up wiring board recited in claim 9, since one via hole consists of two wiring paths, twice as many the wiring paths as the via holes can be passed through the interlayer resin insulating layers, thereby making it possible to provide wirings on the multilayer build-up wiring board with high concentration.
According to claim 10, a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, respectively, the multilayer wiring layer formed on a core substrate, said conductor layers electrically connected to conductor layers on back side of the core substrate by through holes formed in the core substrate, respectively, is characterized in that
a plurality of wiring paths are provided in each of the through hole in said core substrate; and
via holes consisting of a plurality of wiring paths each connected to each of said wiring paths of said through hole are provided right on said through holes in which said plurality of wiring paths are provided.
On the multilayer build-up wiring board recited in claim 10, since a plurality of wiring paths are arranged in one through hole, several times as many the wiring paths as the through holes can be passed through the core substrate. Also, since the via hole provided right on the through hole consists of a plurality of wring paths, several times as many the wiring paths as the via holes can be passed through the interlayer resin insulating layers. This makes it possible to provide wirings on the multilayer build-up wiring board with high concentration. Besides, due to the fact that via holes are formed right on the through holes, the wiring length becomes shortened and it is possible to deal with the demand of providing a high-speed multilayer build-up wiring board.
Furthermore, even if a build-up wiring layer is provided on one side of the core substrate, several times as many wiring paths as through holes can be passed through the core substrate since a plurality of wiring paths are arranged in one through core. Thus, the degree of freedom for the wirings on opposite side to that on which the build-up layer is provided enhances.
According to claim 11, a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, the multilayer wiring layer formed on both sides of a core substrate, conductor layers of the both sides of said core substrate electrically connected to one another by through holes formed in the core substrate, is characterized in that
a plurality of wiring paths are provided in each of the through holes in said core substrate; and
via holes consisting of a plurality of wiring paths each connected to each of said wiring paths of said through hole are provided right on said through holes in which said plurality of wiring paths are provided.
On the multilayer build-up wiring board recited in claim 11, since a plurality of wiring paths are arranged in one through hole, several times as many the wiring paths as the through holes can be passed through the core substrate. Also, since the via hole provided right on the through hole consists of a plurality of wiring paths, several times as many the wiring paths as the via holes can be passed through the interlayer resin insulating layers. This makes it possible to provide wirings on the multilayer build-up wiring board with high concentration. Besides, due to the fact that via holes are formed right on the through holes, the wiring length becomes shortened and it is possible to deal with the demand of providing a high-speed multilayer build-up wiring board.
In this case, since a plurality of wiring paths are arranged in one through hole, several times as many the wiring paths as the through holes can be passed through the core substrate. Due to this, wirings can be integrated on the multilayer wiring layers formed on the front side of the core substrate and those formed on the back side thereof at the same pace. Thus, the number of layers can be minimized by setting the number of the upper multilayer wiring layers to be the same as that of the lower multilayer wiring layers.
According to claim 12, a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, the multilayer wiring layer formed on both sides of a core substrate, conductor layers of the both sides of said core substrate electrically connected to one another by through holes formed in the core substrate, is characterized in that
a filler is filled in the through holes of said core substrate and a conductor layer covering an exposed surface of the filler from the through holes is formed in the through hole;
the through holes and the conductor layers are divided into a plurality of parts, respectively; and
via holes consisting of wiring paths connected to the divided parts of the conductor layers, respectively, are provided right on the through holes covered with said divided parts of the conductor layers.
The multilayer build-up wiring board recited in claim 12 is characterized in that filler is filled in the through holes provided in the core substrate, the conductor layer for covering the exposed surface of the filler from the through holes is formed and the via hole is connected to the conductor layer, thereby ensuring the connection between the build-up wiring layers and the through holes.
According to this constitution, the regions right on the through holes function as inner layer pads, thereby eliminating a dead space. Besides, since it is not necessary to arrange inner layer pads for connecting to via holes from the through holes, the land of the through hole can be formed into a complete round. As a result, the arrangement concentration of the through holes provided in the multilayer core substrate can enhance, the number of through holes can be increased, and the signal lines of the build-up wiring layers at the back side can be connected to the build-up layers on the front side through the through holes. The high concentration of the multilayer build-up wiring boards can be attained by arranging a plurality of wiring paths in each of the increased number of through via holes and by arranging a plurality of the wiring paths in each of the via holes.
On the multilayer build-up wiring board recited in claim 12, the filler filled into the through holes preferably consists of metal particles and thermosetting or thermoplastic resin.
On the multilayer build-up wiring board recited in claim 12, the filler preferably consists of metal particles, thermosetting resin and a hardening agent, or consists of metal particles and thermoplastic resin. Solvent maybe added thereto if required. Since the filler contain metal particles, the metal particles are exposed by sanding the surface thereof and the plated film of a conductor layer formed on the filler is integrated with the filler through the metal particles. Thus, even under strict conditions of high temperature and high humidity such as a PCT (pressure cooker test), the filler is peeled off less frequently at the interface with the conductor layer. In addition, the filler of this type is filled in the through holes each having a metal film formed on a wall surface thereof, so that the migration of metal ions does not occur.
As for metal particles, copper, gold, silver, aluminum, nickel, titanium, chromium, tin/lead, palladium, platinum and the like may be used. The diameter of a metal particle is preferably 0.1 to 50 xcexcm. The reason is as follows. If the diameter is less than 0.1 xcexcm, the copper surface is oxidized and with wetness resin deteriorates. If the diameter exceeds 50 xcexcm, printing property deteriorates. The compounding quantity of the metal particles is preferably 30 to 90 wt %. If it is less than 30 wt %, the adhesion of the cover plating deteriorates and if it exceeds 90 wt % printing property deteriorates.
As for resin to be used, epoxy resin such as bisphenol A resin and bisphenol F resin, phenol resin, polyimide resin, fluorine-contained resin such as polytetrafluoroethylene (PTFE), bismaleimide/triazine (BT) resin, FEP, PFA, PPS, PEN, PES, nylon, aramid, PEEK, PEKK, PET and the like can be used.
As for the hardening agent, an imidazole hardening agent, a phenol hardening agent, an amine hardening agent and the like can be used.
As for solvent, NMP (normal methyl pyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerol, water, 1-, 2 or 3-cyclohexanol, cyclohexanone, methyl cellosolve, methyl cellosolve acetate, methanol, ethanol, butanol, propanol, and the like can be used.
The filler is preferably non-conductive. This is because non-conductor filler has low hardening/contraction rate and the filler is peeled off less frequently from the conductor layer or via hole.
After diligently pursuing their studies to realize the above objects, the present inventors finally reached the invention the outline of which will be described below.
That is, a wiring board recited in claim 13 having a conductor circuit including a conductor layer of two-layer structure in which a second metal film, thinner than a first metal film is provided on said first metal film, is characterized in that
sides of the second metal film forming said conductor layer protrude outside compared with sides of said first metal film.
Furthermore, a multilayer build-up wiring board recited in claim 14 having a structure in which at least one resin insulating layer and at least one conductor circuit are formed on a resin substrate, characterized in that
at least one layer of said conductor circuit includes a conductor layer of two layer structure in which a second metal film, thinner than a first metal film is provided on said first metal film; and
sides of the second metal film forming said conductor layer protrude outside compared with sides of said first metal film.
According to the constitution recited in claim 13, the sides of the second metal film formed on the first metal film protrude outside compared with those of the first metal. Owing to this, if a resin insulating layer is formed on these conductor layers and temperature change and the like occurs due to this protruding structure, stress does not concentrate on the corners of the conductor layer, with the result that it is possible to prevent cracks from occurring to the resin insulating layer.